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LTC1426 Micropower Dual 6-Bit PWM DAC
FEATURES
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DESCRIPTION
The LTC(R)1426 is a dual micropower 6-bit PWM DAC featuring versatile PWM outputs and a flexible pushbutton compatible digital interface. The DAC outputs provide a PWM signal that swings from 0V to VREF, allowing the fullscale output to be varied by adjusting the voltage at VREF. The PWM output frequency is typically 5kHz, easing output filtering requirements. VCC supply current is typically 50A and drops to 0.2A in shutdown. The LTC1426 can be controlled using one of two interface modes: pushbutton and pulse. The LTC1426 automatically configures itself into the appropriate mode at startup by monitoring the state of the CLK pins. In pushbutton mode, the CLK pins can be directly connected to external pushbuttons to control the DAC output. In pulse mode, the CLK pins can be connected to CMOS compatible logic. The DAC outputs initially power up at half scale and the contents of the internal DAC registers are retained in shutdown. The LTC1426 is available in 8-pin MSOP and SO packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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Wide Supply Range: 2.7V VCC 5.5V Wide Reference Voltage Range: 0V to 5.5V Two Interface Modes: Pulse Mode (Increment Only) Pushbutton Mode (Increment/Decrement) Low Supply Current: 50A 0.2A Supply Current in Shutdown Available in 8-Pin MSOP and SO Packages DAC Contents Are Retained in Shutdown DACs Power-Up at Midrange Low Output Impedance: < 100 Output Frequency: 5kHz Typ
APPLICATIONS
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LCD Contrast and Backlight Brightness Control Power Supply Voltage Adjustment Battery Charger Voltage and Current Adjustment GaAs FET Bias Adjustment Trimmer Pot Elimination
TYPICAL APPLICATION
Pushbutton Adjustable CCFL/LCD Contrast Generator
UP TO 6mA LAMP HIGH VOLTAGE ROYER 16 15 14 13 12 11 10 9 5V C9 2.2F 8V TO 28V
5V
R1 44.2k 1% C1 0.1F
R2 44.2k 1% C2 1F C7 1F
ICCFL = 0A TO 50A 1 2 3 4 5 6 CCFL PGND CCFL VSW ICCFL DIO CCFL VC AGND SHDN LT1182 BULB BAT ROYER VIN FBP FBN LCD VSW
RP1 47k UP
RP2 47k UP CONTRAST UP/DOWN 1 CCFL UP/DOWN 2 3
RSHDN 1M SHDN LTC1426 CLK1 CLK2 GND SHDN VCC VREF 8 7 6 5 R5 20k 1%
DOWN
DOWN 4
PWM1 PWM2 R3 5.1k 1% R4 4.99k 1% C3 10F
C8 0.68F
7 LCD VC R7 8 LCD PGND 10k
C4 0.1F
R6 40k 1%
CONSULT THE LT1182 DATA SHEET FOR DETAILS ON THE HIGH VOLTAGE ROYER AND LCD CONTRAST CONVERTER SECTIONS
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C10 2.2F 35V
+
C11 2.2F 35V
LCD CONTRAST CONVERTER VOUT NEGATIVE LCD CONTRAST VOUT = -10V TO -30V
1426 TA01
1
LTC1426
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW CLK1 1 CLK2 2 GND 3 PWM1 4 8 SHDN 7 VCC 6 VREF 5 PWM2
Total Supply Voltage (VCC) ........................................ 7V Reference Voltage (VREF) ............................... - 0.3 to 7V Input Voltage (All Inputs) .............. - 0.3 to (VCC + 0.3V) DAC Output Short-Circuit Duration.................. Indefinite IPWM(MAX) .......................................................... 100mA Operating Temperature Range LTC1426C................................................ 0C to 70C LTC1426I........................................... - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1426CMS8 LTC1426CS8 LTC1426IS8 MS8 PART MARKING LTBQ S8 PART MARKING 1426 1426I
MS8 PACKAGE S8 PACKAGE 8-LEAD PLASTIC MSOP 8-LEAD PLASTIC SO
TJMAX = 100C, JA = 200C/ W (MS8) TJMAX = 100C, JA = 130C/ W (S8)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VCC VREF ICC Supply Voltage Reference Voltage Supply Current CONDITIONS
TA = 25C, (Note 2) unless otherwise specified.
MIN
q q
TYP
MAX 5.5 5.5
UNITS V V A A A A A A bits kHz kHz % %
2.7 0 40 50 0.2 75 75 0.2 6 3 2 5 5 20 98.44 0
Pulse Mode: VSHDN = VCC, VCLK1 = VCLK2 = 0V, PWM1 = PWM2 = NC Pushbutton Mode: VSHDN = VCC, VCLK1 = VCLK2 = PWM1 = PWM2 = NC SHDN = 0 (Note 3) Pulse Mode: VSHDN = VCC, VCLK1 = VCLK2 = 0V, PWM1 = PWM2 = NC Pushbutton Mode: VSHDN = VCC, VCLK1 = VCLK2 = PWM1 = PWM2 = NC SHDN = 0 (Note 3) 0C TA 70C - 40C TA 85C VCC = 2.7V, VREF = 0.5V
q q q q q q
100 100 10 150 150 10 6 6 100
IREF
Reference Current
DAC Resolution DAC Frequency DAC Output Impedance DAC Full-Scale Duty Cycle DAC Zero-Scale Duty Cycle DNL INL FS Error IIN DAC Differential Nonlinearity DAC Integral Nonlinearity DAC Full-Scale Error Logic Input Current Pulse Mode: 0V VIN VCC Pushbutton Mode: 0V VIN VCC VIH CLK High Level Input Voltage (Note 5) VCC = 5.5V VCC = 3.6V SHDN CLK1, CLK2 SHDN CLK1, CLK2 SHDN CLK1, CLK2 SHDN CLK1, CLK2 Monotonicity Guaranteed (Note 4) (Note 4)
q q q q q q q q q q q q q q
0.05 0.05 0.50 5 5 5 10 2.0 4.4 1.9 2.9
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LSB LSB LSB A A A A V V V V
LTC1426
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VIL CLK Low Level Input Voltage (Note 5) CONDITIONS VCC = 4.5V VCC = 2.7V IOZ ZIN fCLK tCKHI tCKLO tPW tDEB tDELAY fREPEAT Three-State Output Leakage CLK Input Resistance Clock Frequency Clock High Time Clock Low Time Pulse Width Debounce Time Repeat Rate Delay Repeat Frequency SHDN = 0
TA = 25C, (Note 2) unless otherwise specified.
MIN SHDN CLK1, CLK2 SHDN CLK1, CLK2
q q q q q
TYP
MAX 0.8 0.8 0.45 0.45 5
UNITS V V V V A M MHz kHz ns ns ns ns s
Pushbutton Mode, CLK1/CLK2 Pulse Mode, VCC = 3.3V Pulse Mode, VCC = 2.7V Pulse Mode, VCC = 3.3V Pulse Mode, VCC = 2.7V Pulse Mode, VCC = 3.3V Pulse Mode, VCC = 2.7V Pushbutton Mode Pushbutton Mode Pushbutton Mode Pushbutton Mode
q q q q q q q q q q
2.5 1 750 450 600 450 600 670 10.7 340 11.7 12.8 410 19.5 21.3 680 23.4
ms ms Hz
The q denotes the specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground, unless otherwise specified. All typicals are given for VCC = VREF = 5V, TA = 25C and PWM1/PWM2 output to GND, CPWM = 10pF.
Note 3: Shutdown current can be negative due to leakage currents if VCC > VREF or VREF > VCC. Note 4: Guaranteed by Design. Decouple the VCC and VREF pins to GND using high quality, low ESR, low ESL 0.1F capacitors to eliminate PWM switching noise that may otherwise get coupled into the CLK1/CLK2 high impedance input buffers. The decoupling capacitors should be located in close proximity to these pins and the ground line to have maximum effect. Note 5: Input thresholds apply for both pushbutton and pulse modes.
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Nonlinearity (DNL)
0.05 VCC = VREF = 5V 0.04 TA = 25C 0.03
DNL ERROR (LSB)
0.05 0.04 0.03 0.02
OUTPUT PULL-DOWN VOLTAGE (mV)
0.02 0.01 0 - 0.01 - 0.02 - 0.03 - 0.04 - 0.05 0 8 16 24 32 40 CODE 48 56 64
ERROR (LSB)
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1426 G01
Integral Nonlinearity (INL)
VCC = VREF = 5V TA = 25C
Output Pull-Down Voltage vs Output Current Sink Capability
1000 VCC = 5V 85C 25C - 40C 10
100
0.01 0 - 0.01 - 0.02 - 0.03 - 0.04 - 0.05 0 8 16 24 32 40 CODE 48 56 64
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0.1 0.1
1 10 100 OUTPUT CURRENT SINK CAPABILITY (mA)
1426 G03
1426 G02
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LTC1426 TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Clock High Time vs Temperature
600 500 400 VCC = 3V 300 200 VCC = 5V 100 0 - 40
SUPPLY CURRENT (A)
SUPPLY CURRENT (A)
CLOCK HIGH TIME (ns)
- 15
10 35 TEMPERATURE (C)
PIN FUNCTIONS
CLK1 (Pin 1): Channel 1 Clock/Pushbutton Input. CLK2 (Pin 2): Channel 2 Clock/Pushbutton Input. GND (Pin 3): Ground. It is recommended that GND be tied to a ground plane. PWM1 (Pin 4): Channel 1 PWM Output. PWM2 (Pin 5): Channel 2 PWM Output. VREF (Pin 6): Voltage Reference Input. VREF powers the DAC output buffers and can be used to control the output span. Bypass VREF to GND with an external capacitor to minimize output errors. VREF can be tied to VCC if desired. VCC (Pin 7): Voltage Supply. This supply must be kept free from noise and ripple by bypassing directly to the ground plane. SHDN (Pin 8): Shutdown. A logic low puts the chip into shutdown mode with the PWM outputs in high impedance. The digital settings for the DACs are retained in shutdown.
TI I G DIAGRA S
Pulse Mode Timing
tCKL0 CLK1 CLK2
1426 TC01
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60
1426 G04
Supply Current vs Logic Input Voltage
38.5 36.5 34.5 32.5 30.5 28.5 26.5 24.5 22.5
85 60
Supply Current vs Temperature
VCC = 5V 50 40 30 20 10 0 - 40 PULSE MODE PUSHBUTTON MODE
PUSHBUTTON MODE
PULSE MODE
TA = 25C CLK1 AND CLK2 TIED TOGETHER 0 1 3 4 2 LOGIC INPUT VOLTAGE (V) 5
1426 F05
- 15
10 35 TEMPERATURE (C)
60
85
1426 G06
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Pushbutton Mode Timing
tPW CLK1 CLK2
tCKHI
1426 TC02
LTC1426
BLOCK DIAGRAM W
POWER-ON RESET LATCH AND LOGIC MODE SELECT 0 = PUSHBUTTON MODE 1 = PULSE MODE VREF 6 COMPARATOR DRIVER PWM1 6-BIT UP/DOWN COUNTER CONTROL LOGIC 6-BIT UP/DOWN COUNTER 6-BIT UP COUNTER 6 COMPARATOR 6 DRIVER PWM2 SHDN OSCILLATOR
1426 F01
CLK1 CLK2
INPUT CONDITIONING
DEBOUNCE CIRCUIT
Figure 1. LTC1426 Block Diagram
DEFI ITIO S
LSB: The least significant bit or the ideal duty cycle difference between two successive codes. LSB = DCMAX/64 DCMAX = The DAC output maximum duty cycle Resolution: The resolution is the number of DAC output states (64) that divide the full-scale output duty cycle range. The resolution does not necessarily imply linearity. INL: End point integral nonlinearity is the maximum deviation from a straight line passing through the end points of the DAC transfer curve. The INL error at a given code is calculated as follows: INL = (DCOUT - DCIDEAL)/LSB DCIDEAL = (Code)(LSB) DCOUT = the DAC output duty cycle measured at the given number of clocked in pulses. DNL: Differential nonlinearity is the difference between the measured duty cycle change and the ideal 1LSB duty cycle change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (DCOUT - LSB)/LSB DCOUT = The measured duty cycle difference between two adjacent codes. Full-Scale Error: Full-scale error is the difference between the ideal and measured DAC output duty cycles with all bits set to one (Code = 63). The full-scale error is calculated as follows: FSE = (DCOUT - DCIDEAL)/LSB DCIDEAL = DCMAX
APPLICATIONS INFORMATION
Dual 6-Bit PWM DAC Figure 1 shows a block diagram of the LTC1426. Each 6-bit PWM DAC is guaranteed monotonic and is digitally adjustable in 64 equal steps, which corresponds from 0% to 98.5% duty cycle full scale. At power-up, the counters reset to 100000B and both DAC outputs assume midscale duty cycle. The PWM outputs have an output impedance of less than 100. The DAC outputs swing from 0V to the reference voltage, VREF, which can be biased from 0V to 5.5V. The frequency of the DAC outputs is above 3kHz, easing output filtering. In the case of a pure resistive load, the voltage measured across load RL is given by: V = (VPWM)RL/(RL + ROUT)
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LTC1426
APPLICATIONS INFORMATION
where VPWM is the no load DAC output voltage, RL is the resistive load and ROUT is the DAC output impedance. Therefore, the resistive load RL should be sufficiently large to ignore the effect of output impedance on the load voltage. Figure 2 shows a typical lowpass filter recommended to filter the PWM outputs. Without filtering, results obtained from unfiltered outputs can be erroneous when taking measurements from a voltmeter. The ratio of the filter time constant, t, to the PWM frequency determines the amount of output ripple frequency that feeds into the system. In addition, the loading of the output also determines an additional error voltage drop across R1.
R1 10k INPUT C1 0.1F OUTPUT
1426 F02
Figure 2. Lowpass Filter for PWM Averaging
Digital Interface The LTC1426 can be controlled by using one of two interface modes: pulse mode and pushbutton mode. The operating interface mode is determined during powerup. If both CLK1 and CLK2 inputs are floating on power-up, then an interface mode detect circuit configures the chip in pushbutton mode until the next VCC reset (Figure 3). However, if either of CLK1 or CLK2 is at logic 0 or 1 at
CLK1 CLK2
TYPICAL APPLICATIONS N
Typical applications for this part include digital calibration, industrial process control, automatic test equipment, cellular telephones and portable battery-powered applications. Figures 4 and 5 show how easy this part is to use. In all applications, the PWM full-scale output voltage is set by VREF. This makes interfacing convenient when a variety of reference spans are needed. Pulse Mode Figure 4 shows the LTC1426 in a pulse mode, stand-alone application. The LTC1426 can interface directly with minimum external components to most popular microPWM1
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power-up, then the chip configures in pulse mode until the next VCC reset. Figure 3 shows the simplified logic for determining the interface mode at power-up. A set of pull-up/pull-down resistors allow the LTC1426 to sense the state of the CLK pins at power-up. If both CLK1 and CLK2 pins are floating on power-up then the control signal from the LTC1426 leaves these resistors in place, allowing the LTC1426 to detect three operating states at each CLK pin: high, low and "middle" (floating). If the CLK pins are tied to either logic 0 or 1 at power-up, then the control signal will disconnect these resistors, making CLK1 and CLK2 CMOS compatible input pins. Note that both CLK pins will always be in the same mode. If one pin is floating and the other is at logic high/low on power-up, the LTC1426 will assume pulse mode.
VCC
INTERNAL LOGIC CLK1 INPUT CLK2 INPUT CONTROL
LTC1426
1426 F03
Figure 3. Interface Mode Detect Circuit
processors (MPUs). The Intel 8051 was chosen to demonstrate direct interface for the LTC1426, as this
VCC 2.7V TO 5.5V MPU (e.g. 8051) P1.0 P1.1 1 2 3 4 LTC1426 CLK1 CLK2 GND SHDN VCC VREF 8 7 6 VREF 0V TO 5.5V 5 PWM2
1426 F04
0.1F SHDN
PWM1 PWM2
PWM1/PWM2: 0V TO 0.985(VREF)
Figure 4. Stand-Alone Pulse Mode Interface
LTC1426
TYPICAL APPLICATIONS N
microprocessor has "quasi-bidirectional" ports that eliminate additional pull-up resistors to VCC. However, external pull-up resistors should be used if the microprocessor doesn't pull the port pins high during reset. In pulse mode, each clock pulse applied to the CLK1 or CLK2 input increments the respective counter by one count. When the counter increases beyond full scale (111111B), the counter rolls over and becomes zero scale (000000B). In this way, a single pulse applied to the CLK1 or CLK2 input increases the respective counter by one count, and 63 pulses decrease that counter by one count. Pushbutton Mode Figure 5 shows how to use the LTC1426 in a typical pushbutton application. In pushbutton mode, a logic 1 pulse applied to the CLK1 or CLK2 input increments the
VCC 2.7V TO 5.5V R UP R 1 UP 2 3 DOWN DOWN PWM1 4 VCC 2.7V TO 5.5V LTC1426 CLK1 CLK2 GND SHDN VCC VREF 8 7 6 VREF 0V TO 5.5V 5 PWM2 SHDN
PWM1 PWM2
PWM1/PWM2: 0V TO 0.985(VREF)
LIMITING RESISTOR R PREVENTS SHORTING OF VCC AND GND WHEN BOTH BUTTONS ARE SIMULTANEOUSLY PUSHED. THIS RESISTOR CAN BE PLACED EITHER IN THE VCC OR GND LEG AND THIS DETERMINES THE FUNCTION WHEN BOTH BUTTONS ARE PUSHED. VALUE OF R < 50k
Figure 5. Pushbutton Mode Interface
SHDN MPU (e.g. 8051) P1.0 P1.1 1 2 3 4
CLK1 CLK2 GND
PWM1 PWM2
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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respective counter by one count, and stops incrementing when the counter reaches full scale (111111B). A logic 0 pulse applied to the CLK1 or CLK2 input decrements the respective counter by one count, and stops decrementing when the counter reaches zero scale (000000B). An onchip debouncing circuit has a debounce time of 12.8ms to prevent unintended counts with bouncing pushbuttons. After a time delay of 410ms, the counter will begin to increment/decrement at a repeat rate of 19.5Hz if the pushbutton remains pressed. Care should be taken to avoid running the CLK and PWM traces close to one another. Since the CLK pins are high impedance input nodes in pushbutton mode, current spikes caused by the switching of the PWM outputs feedthrough via any stray capacitance between PWM and CLK lines if not properly routed. Use of proper grounding techniques and spacing of these lines are highly recommended for optimal performance. Figure 6 shows a dual digitally programmable current source using the LT (R)1013 dual precision op amp and two NPN transistors (2N3904). After the lowpass filter combination of R1, C1 (R2, C2), its output swings from 0V to 4.93V. In the configuration shown, this voltage will be forced across the resistor RA1 (RA2). If RA1 (RA2) is chosen to be 493, the output current will range from 0mA at zero scale to 10mA at full scale. The minimum voltage for VS is determined by the load resistor RL1 (RL2) and Q1(Q2)'s VCESAT voltage. With a load resistor of 50, the voltage source can be as low as 5V.
0.1F
1426 F05
5V 0.1F
VS RL1
10V 0.1F LT1013 1 RA1 493 OUT A -IN A +IN A V- V+ OUT B - IN B + IN B 8 7 6 5 2 3
VS RL2 2N3904
LTC1426 SHDN VCC VREF 8 7 6 5 R2 10k R1 10k
2N3904
RA2 493
C1 0.1F C2 0.1F
4
1426 F06
IOUT1/IOUT2: 0mA TO 10mA RL1/RL2: < 50 VS: 5V TO 30V
Figure 6. Dual Digitally Programmable Current Source
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LTC1426
TYPICAL APPLICATIONS N
Shutdown Mode Upon the application of a logic low shutdown signal, the entire IC converts to micropower shutdown mode where VCC supply current reduces to less than 0.3A typical. The shutdown function features the data retention of the current PWM1 and PWM2 codes so that upon release from a shutdown condition, these states are reinstated. This is a functional difference in comparison to the half-scale preset for both PWM1 and PWM2 outputs upon power-up.
PACKAGE DESCRIPTION
0.007 (0.18) 0.021 0.004 (0.53 0.01)
0 - 6 TYP 0.192 0.004 (4.88 0.10) 0.025 (0.65) TYP 1 23 4
MSOP08 0595
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254)
0- 8 TYP 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157** (3.810 - 3.988)
0.016 - 0.050 0.406 - 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER
LT1182/LT1183 LTC1257
DESCRIPTION
CCFL/LCD Contrast Switching Regulators Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V. Reference Can Be Overdriven Up to 12V, i.e., FS Max = 12V Micropower IOUT 8-Bit Current DAC Dual, Serial I/O VOUT 12-Bit DAC in SO-8 Complete Serial I/O VOUT 12-Bit DACs Dual, Serial I/O Multiplying IOUT 12-Bit DAC Serial I/O Mulitplying IOUT 12-Bit DAC
LTC1329/LTC1329-10/LTC1329-50 LTC1446/LTC1446L LTC1451/LTC1452/LTC1453 LTC1590 LTC8043
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417 q (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com
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Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.040 0.006 (1.02 0.15) 0.006 0.004 (0.15 0.10) 0.118 0.004* (3.00 0.10) 8 76 5
0.012 (0.30)
0.118 0.004** (3.00 0.10)
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.053 - 0.069 (1.346 - 1.752) 0.004 - 0.010 (0.101 - 0.254) 8 0.189 - 0.197* (4.801 - 5.004) 7 6 5
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) BSC
SO8 0695
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COMMENTS
3V to 30V Single Supply in 16-Pin SO 5V to 15V Single Supply, Complete VOUT DAC in SO-8
2.7V to 6.5V Single Supply in SO-8 Rail-to-Rail VOUT, 5V/3V Single Supply Rail-to-Rail VOUT, 3V/5V Single Supply in S0-8 5V Single Supply in 16-pin SO Package 5V Single Supply in SO-8
1426f LT/GP 0597 7K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1997

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